The present invention generally relates to semiconductor devices, and more particularly to a semiconductor memory device having a memory cell capacitor for storage of information and a fabrication process thereof.
Dynamic random access memories (DRAM) use memory cell capacitors for storing binary information in the form of electric charges. The memory device includes a number of memory cells, and each memory cell includes therein a MOS transistor having a gate connected to a word line, a source connected to a bit line and a drain connected to a memory cell capacitor. Upon energization of the word line and bit line, the electric charges are transferred from the memory cell capacitor to the bit line when reading data. When writing data, the word line is energized and the electric charges are transferred from the bit line to the memory cell capacitor. The minute voltage change appearing on the bit line in response to the electric charge transfer at the time of reading is then detected by a sense amplifier.
The memory cell capacitor generally comprises a polysilicon electrode body on which a thin dielectric film is deposited, and an opposing electrode is further deposited on the dielectric film such that the dielectric film is sandwiched between the polysilicon electrode body and the opposing electrode. The polysilicon electrode body is connected to the drain of the MOS transistor of the memory cell while the opposing electrode is connected to the ground.
With the requirement of increased memory capacity of semiconductor memories, the integration density of the semiconductor memories is increasing continuously. Such an increase in the integration density inevitably causes a reduction in the size of the polysilicon body used for the memory cell capacitor, and there occurs a problem in that the capacitance of the memory cell capacitor is not sufficient for storing data.
FIG. 1 shows a conventional semiconductor memory device 10 in the plan view while FIG. 2 shows the cross section of the device of FIG.1 along a line 2'--2'in FIG. 1.
Referring to FIGS.1 and 2, there is provided a substrate 11 that is covered by a field oxide region 12 except for a device region 14 on which a memory cell transistor 16 is formed. In the plan view of FIG. 1, the device region 14 is defined by a boundary 14a.
In the illustrated example, the substrate 11 is doped to the p-type and diffusion regions 18 and 20, both of the n-type, are formed within the substrate 11 in correspondence to the device region 14, as the source and drain of the memory cell transistor 16. Thereby, a p-type channel region 19 is formed in the substrate between the diffusion regions 18 and 20.
In correspondence to the channel region 19, there is provided a gate insulation film 22 and a polysilicon gate electrode 24 is provided on the gate insulation film 22 as usual. The gate electrode 24 is embedded in an insulation layer 26 and extends generally in the column direction in FIG.1 as a word line WL. In correspondence to where the word line WL passes through the device region 14, the word line WL extends in the vicinity of the substrate 11 as the gate electrode 24 as described previously, while the word line WL is located on the field oxide region 12 in the rest of the device.
As usual in the memory cell transistor, the diffusion region 18 is exposed at the surface of the substrate 11 via a contact hole 28 formed in the insulator layer 26 to penetrate through the gate insulator film 22, and a bit line BL extending in the row direction in the plan view of FIG. 1 contacts to the exposed diffusion region 18 via the contact hole 28.
The bit line BL is buried under an insulator layer 30, and a contact hole 32 is provided through the insulator layer 30 as well as through the underlying insulator layer 26 and the gate insulator film 22, such that the diffusion region 20 forming the drain of the memory cell transistor 16 is exposed. In contact with the exposed diffusion region 20, there is provided a polysilicon body 34 on the insulator layer 30 as the accumulation electrode of a memory cell capacitor 36.
As shown in the plan view of FIG. 1, the memory cell capacitor 36 has a generally rectangular form. Associated therewith, the polysilicon body 34 has a corresponding rectangular form. The polysilicon body 34 has a generally undulated top surface in correspondence to the contact hole 32, while the lateral surface of the body 34 extends straight in the lateral as well as vertical directions. The top surface and the side surface of the polysilicon body 34 are covered by a thin dielectric film 38, typically with a thickness of 60 A, and a polysilicon layer 40, acting as an electrode opposing the accumulation electrode 34 of the memory cell capacitor, is provided on the dielectric film 38.
Further, an insulator layer 42 having a planarized top surface is provided on the polysilicon layer 40, and an aluminum layer 44 is provided on the insulator layer 42 for the interconnection within the device. The cross sectional view of FIG.2 shows the state before the aluminum layer 44 is patterned for forming the wiring pattern. Thus, one can see a photoresist layer 46 provided on the aluminum layer 44. The insulator layer 42 may be formed from a PSG.
In such a memory cell device, the area that is occupied by the memory cell capacitor 36 in the plan view decreases with increasing integration density. Associated therewith, there is a tendency that the height of the polysilicon body 34 and hence the height of the memory cell capacitor 36 is increased in order to secure sufficient capacitance of the capacitor 36. However, such an increase in the height of the memory cell capacitor causes an increase in the level of the planarized top surface of the insulator layer 42 and hence the level of the aluminum layer 44 that is to be patterned using the photoresist layer 46 as the mask.
It should be noted that the semiconductor memory device in general has peripheral devices 48 such as address buffers, row and column decoders, sense amplifiers, input and output buffers, and the like at the peripheral part of the device, and the interconnection to these peripheral devices is formed also by patterning the aluminum layer 44. In patterning the aluminum layer 44, it is necessary to conduct an exposure process to expose the photoresist layer 46 to an ultraviolet radiation that is passed through a suitably patterned mask.
As the memory cell capacitor 36 projects upward, the level of the photoresist layer 46 differs in the memory cell region located above the memory cell transistors 16 or capacitors 36 and in the peripheral region located above the peripheral device 48. Thereby, there appears a level difference d as illustrated. With the increase in the integration density, the upward projection of the memory cell capacitor 36 increases as already described, and the level difference d increases accordingly.
With the difference d thus increased, there occurs a difficulty in focusing the ultraviolet beam properly at the time of exposure of the photoresist layer 46. More specifically, there arises a problem in that the radiation of the ultraviolet beam on the photoresist layer 46 becomes insufficient in the peripheral region when the ultraviolet beam is focused on the photoresist layer 46 of the memory cell region. When the ultraviolet beam is focused on the peripheral region, on the other hand, the radiation on the memory cell region becomes insufficient, In order to achieve the satisfactory focusing of the ultraviolet radiation beam for both the memory cell region and the peripheral region, it is necessary to increase the focal depth of the optical system used for focusing the beam. However, such an increase in the focal depth inevitably invites a degradation of resolution as will be examined closely hereinafter.
Generally, the focal depth of an optical system is given by the equation EQU focal depth.infin..lambda.N.sub.A.sup.2
where .lambda. stands for the wavelength of an optical beam that is focused by the optical system and N.sub.A represents the numeric aperture of the optical system used for focusing.
On the other hand, the resolution limit achieved by such an optical system is given as EQU resolution limit.infin..lambda.N.sub.A.
As can be seen from the latter equation, the resolution limit decreases with decreasing wavelength and increasing numeric aperture N.sub.A. In other words, by using a shortwave radiation and an optical system having a large numeric aperture N.sub.A, one can produce smaller patterns. However, such a selection inevitably causes a decrease in the focal depth as can be seen in the former equation and hence the difficulty in focusing the optical beam simultaneously on the photoresist 46 covering the memory cell region and on the photoresist 46 covering the peripheral region.
FIG. 3(A) shows the polysilicon body 34 and FIG. 3(B) shows a schematic representation of the polysilicon body 34, as a rectangular body characterized by lateral edges a and b and a height d.
In the memory cell capacitor 36 formed on such a polysilicon body 34, the capacitance C is given as EQU C=S.multidot..epsilon./t
where .epsilon. represents the dielectric constant of the dielectric film 38, S represents the surface area of the polysilicon body 34 covered by the dielectric film 38, and t represents the thickness of the dielectric film 38.
In the semiconductor memory device having the 64 Mbit memory capacity (64M DRAM), a capacitance of about 30 fF is required for the value of C for storage of information, while the parameter .epsilon./t is set to about 7 fF/.mu..sup.2. It should be noted that the parameter .epsilon. is determined by the material of the dielectric film and cannot be increased as desired. The thickness t, too, cannot be decreased excessively, as the film 38 has to cover the top surface as well as the side surfaces of the polysilicon body 34 uniformly and without interruption.
Under the circumstances, one needs to secure a surface area of about 4 .mu..sup.2 for the value of S. In the 64M DRAM device where the edges a and b of FIG. 3(B) are set generally to 1.4 .mu.m and 0.6 .mu.m, this means that a size of about 0.8 .mu.m is necessary for the value of the height d. It should be noted that the surface area S is given as S=a.times.b+2(a+b).times.d, assuming the rectangular memory cell capacitor. On the other hand, a resolution limit of about 0.3 .mu.m or less is needed for patterning such a memory device. Thereby, the focal depth cannot become larger than 1 .mu.m.
It should be noted that the difference between the focal depth and the height d is only 0.2 .mu.m in the above case. This means that the fabrication of the 64M DRAM according to the foregoing procedure is extremely difficult. On the other hand, use of the ultraviolet exposure process described above is preferable for its high throughput and is particularly suited for the mass production of the low cost semiconductor memories. In order to eliminate this problem, various efforts are made to increase the surface area S of the memory cell capacitor without increasing the height d.
FIG. 4 shows a construction proposed previously by the applicant in the U.S. Pat. No. 4,910,566 for increasing the surface area S of the memory cell capacitor. In this construction, a generally rectangular depression 34.sub.1 is formed in the rectangular polysilicon body 34. For example, by setting the size of edges a' and b' of the depression 34.sub.1 to be 1.2 .mu.m and 0.4 .mu.m and by setting the size of the edge d' to be smaller than the height d by 0.1 .mu.m, one can attain the foregoing surface area S of 4 .mu..sup.2 while maintaining the height d at about 0.5 .mu.m. In this case, the simultaneous exposure of the photoresist layer 46 in the memory cell region and in the peripheral region is allowed. However, such a process is obviously complex and is not suited for the mass production of the memory cell device.
FIG. 5 shows another conventional proposal for increasing the surface area S of the memory cell capacitor disclosed in the U.S. Pat. No. 4,742,018. In this proposal, projections and depressions are formed on the upper surface of the polysilicon body 34 for increasing the surface area S. This construction, too, is complex and has a problem in mass producing the semiconductor memory cell device.
FIG. 6 shows still another conventional proposal for increasing the surface area S of the memory cell capacitor (see, for example, Yoshimura et al., IEDM Tech. Dig. p.596, 1988). In this prior art, a hemispherical grain silicon (HSG-Si) layer is grown on a polysilicon body 34 that forms the electrode. As the HSG-Si layer has an irregular surface morphology, the surface area of the electrode is significantly increased. This approach, however, has a problem of reliability of the capacitor, as there are a number of sharp projections formed on the surface of the electrode. Such sharp projections tend to invite a concentration of the electric field in the thin dielectric film 38 when the dielectric film is deposited on such an irregular surface. Further, the fabrication process of such a structure is difficult, particularly with respect to the control of the etching process for selectively removing the deposited HSG-Si layer from the device surface except for the surface of the polysilicon body 34.
Thus, there is an acute demand for the design of high density semiconductor memory device that can be fabricated by the ultraviolet exposure process with sufficient capacitance of the memory cell capacitor while maintaining the height of the memory cell capacitor small.